1. Field of the Invention
The subject invention is related to gated oscillators and, more particularly, to gated oscillator circuits for forming sampling clock signals for digital signal processing.
For example, in digital processing of a television signal, it is necessary to take a given number of samples for each horizontal scanning line. For example, the NTSC system defines a sampling frequency of 910 Fh, where Fh is the horizontal scanning frequency and is equal to 15,734.26573 Hz., giving a sampling frequency Fs of 14,318,181.82 Hz. and a sampling time EQU Ts=1/Fs=69.841269 ns.
If it is assumed that the active line time is 53.0095 us., then the number of active samples N is 759, that is, there are 759 samples of active video for each horizontal line. To do this, it is necessary to have a device which generates a sample command every 69.84 ns. after the horizontal blanking indicates the beginning of the active horizontal line time. In particular, what is needed is an oscillator which can be started and stopped by the horizontal blanking signal.
2. Description of Related Art
In prior art devices, the sampling clock has been provided using a gated RC relaxation oscillator. The circuit shown in FIG. 1 is one of many that has been used. Before power is applied, the gate input and output are at ground potential and capacitor C is discharged. When power is applied, the output goes high and capacitor C charges through resistor R until the level Vdd is reached (see FIG. 2). At this point, when the gate input goes high, the output goes low discharging the capacitor C causing the voltage thereacross to drop to the level Vn, whereupon the output goes high again charging the capacitor C raising the voltage to the level Vp. The voltage across the capacitor C and the output therefore alternately swing back and forth between Vn and Vp until the gate input goes low. Then the output goes high and further operation is halted. The capacitor C then is charged, through the resistor R, back to the level Vdd readying the oscillator for reuse.
The oscillator period is given by:
T=T1+T2 PA1 T1=R(C)Ln((Vdd-Vn)/(Vdd+Vp)) PA1 T2=R(C)Ln(Vp/Vn)
Since R, Vp and Vn can vary with temperature and voltage changes, T1 and T2 can also vary. Thus the frequency is not very stable. Also, the exact switching point of the output with respect to Vp or Vn is modulated with the ever present circuit noise. This causes the edge of the output at switching to change slightly or jitter in a random fashion. The edge jitter or noise is characteristic of relaxation type oscillators.